8-bit 22nW SAR ADC using output offset cancellation technique

Authors

Karim M. Abozeid, The British University in EgyptFollow
M. M. Aboudina, Cairo UniversityFollow
A. H. Khalil, Cairo UniversityFollow

Document Type

Conference Proceeding

Publication Date

Winter 12-29-2015

Abstract

In this paper we present an offset cancellation technique for a comparator used in SAR (successive approximation register) analog to digital converter improving the signal to noise ratio of the whole system with minimum power consumption at the expense of complexity of the system. An 8-bit SAR ADC is presented with power consumption 22nW, ENOB = 7.051 and SNR = 47.11 dB. All simulations are done under clock frequency = 100 kHz and a supply voltage 1V.

Comments

doi: 10.1109/ICENCO.2015.7416328.

Recommended Citation

K. M. Abozeid, M. M. Aboudina and A. H. Khalil, "8-bit 22nW SAR ADC using output offset cancellation technique," 2015 11th International Computer Engineering Conference (ICENCO), Cairo, 2015, pp. 76-79, doi: 10.1109/ICENCO.2015.7416328.